1. Field of the Invention
This invention relates to computer processors and, more particularly, to controlling requests to read data from and write data to memory.
2. Description of the Related Art
Microprocessors have evolved to include a variety of features aimed at improving the speed and efficiency with which instructions are executed. In addition to advances in clock speed and the resulting reduction in instruction execution time, microprocessors may include pipelines, multiple cores, multiple execution units, etc. that permit some degree of parallel instruction execution. Further performance improvements have also been realized through a variety of buffering, queuing, and caching features intended to overcome bottlenecks in the movement of data to and from system memory. For example, microprocessors often include multiple memory caches, arranged hierarchically and shared by multiple cores or execution units. Since cache accesses are faster than memory accesses, various caching techniques are used to increase the likelihood that data is located in a cache when needed by a core or execution unit.
Despite the improvements noted above, there remains room for optimization of the bandwidth and latency involved in accessing system memory. For instance, in a typical computer system in which a processor may include a memory controller coupled to system memory through a memory bus, it may be advantageous to optimize the bandwidth on the memory bus by accumulating memory requests in a queue and periodically re-ordering the queue contents. Different types of memory requests have different requirements for bandwidth and/or latency. Various prioritization strategies have been tried to address these concerns.
One way to optimize latency takes note of the fact that a prefetch from memory may have no stringent latency requirement whereas it may be highly desirable to minimize latency for a demand read request to the same address. Consequently, prefetches may be assigned a lower priority then demand read requests. Unfortunately, low-priority prefetches may accumulate in the queue and be bypassed by higher-priority demand read requests. Accumulated prefetches may then only be processed if there are no higher priority requests in the queue.
Another optimization attempts to account for any reduction in effective bandwidth achievable on the memory bus that may be caused by the time to switch between read and write accesses. Conventionally, write requests may be given lower priority than read requests since read requests have more stringent latency requirements. Unfortunately, write requests may accumulate in the queue while being bypasses by higher-priority read requests, to be processed only if no higher priority requests are in the queue.
The latency requirement of isochronous memory requests are another concern that may provide an opportunity for optimization. These requests may be able to tolerate long latencies as long as a maximum latency is not exceeded. Otherwise, dropped video frames and/or audio popping may occur. Typically, isochronous latency requirements are addressed by assigned a high priority compared to other traffic. Unfortunately, this may cause normal read requests to be bypassed in the queue even when pending isochronous request are well below their latency maximum. In addition, arrival of a high priority isochronous request may cause a new page to be opened while lower priority requests for an already opened page are bypassed, causing the opened page to be closed and resulting in poor page management performance.
In order to address the above concerns, what is desired is a way to flexibly prioritize memory requests that is sensitive to the latency and bandwidth requirements of various types of memory requests.